Hardware implementation of an asynchronous analog neural network with training based on unified cmos ip blocks

An approach to designing neuromorphic electronic devices based on convolutional neural networks with backpropagation training is presented. The approach is aimed at improving the energy efficiency and performance of autonomous systems. The developed approach is based on the use of a neural network topology compiler based on five basic CMOS blocks intended for analog implementation of all computational operations in training and inference modes. The developed crossbar arrays of functional analog CMOS blocks with digital control of the conductivity level ensure the execution of the matrix-vector multiplication operation in the convolutional and fully connected layers without using the DAC and using the ADC in the synaptic connection weight control circuits only in the training mode. The effectiveness of the approach is demonstrated by the example of the digit classification problem solved with an accuracy of 97.87 % on test data using the developed model of hardware implementation of an asynchronous analog neural network with training.